1. Field of the Invention
The invention relates to a method of fabricating CMOS (Complementary Metal-Oxide-Semiconductor) transistors, and more particularly, to a method of fabricating CMOS transistors with planar shallow trench isolations.
2. Description of the Prior Art
In the present days, shallow trench isolation (STI) structures are recognized as an important configuration to fabricate CMOS transistors because the STI technologies offer lots of advantages. For example, a bird's beak is entirely eliminated and channel-stop dopant redistribution is reduced, and the structure is fully recessed to offer the potential of a completely planar surface when compared with the local oxidation of silicon (LOCOS) technology. In addition, the problem of field-oxide thinning in narrow isolation spaces does not occur. Furthermore, the threshold voltage is constant as a function of channel width because the narrow-channel effect found in LOCOS is also eliminated.
Because the STI structures have attractive advantages, there are amounts of processes continuously disclosed. Perera et al proposed an isolation method using oxide filled shallow trenches focus primarily at isolating CMOS devices and which has been developed for 0.25 .mu.m SRAM (Static Random Access Memory) fabrication (refer to "Trench Isolation for 0.45 .mu.m Active Pitch and Below" in IEDM Tech. Dig. P.679, 1995.) Fazan et al proposed an STI process that a vertical B field implant and forming of disposable spacers are combined to avoid devices reverse narrow width effects (refer to "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs" in IEDM Tech. Dig., p. 57, 1993.) Nag et al show an ICP (Inductive Coupled) HDP--(High Density Plasma) CVD (Chemical Vapor Deposition) process to obtain a low budget and high throughput approach as well as provide good gap-fill, low moisture uptake at 0.3 .mu.m spacing (refer to "Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 .mu.m Technologies" in IEDM Tech. Dig., p841, 1996.)
Typically, a relative shallow trench isolation is first etched to form a recess structure in the silicon substrate, and then refilled with an insulator material. The surface is planarized after refill to complete the isolation structure. However, the STI process is hard to form a planar trench isolation (refer to "A Novel Planarization of Oxide-Filled Shallow-Trench Isolation" in J. Electrochem. Soc., vol., 144, p 315, 1997 disclosed by Cheng et al.), and usually, the STI technology requires a complicated planarization procedure. Conventionally, a combination of dry etch and CMP (Chemical Mechanical Polishing) with an extra mask to prevent dishing in wide field regions has been proposed to planarize a device surface. Another traditional approach applying only dry etch planarization requires a LOCOS isolation in wide field areas that will significantly increase the process complexity. A requirement has been arisen to disclose an STI process that forms CMOS transistors with planar surface and lower budgets.